市廠推廣推廣運營專員 口試地點: 深圳市福田區復興西路華康大廈1棟401室 雇用人數: 1 名 薪資報酬: 面議
活動崗亭主要職責:
1.了解手機元電子電子元件股票市場短信和數值闡發,確定有限有限公司官方網站的獲得營銷策劃標有目標和個人規劃,有限有限公司新網絡媒介物件二戰臺經營管理的個人規劃和修健;
2.走上種種收集整理分銷渠道大力推廣裝修公司寬泛,進行的市場闡發,大力推廣貨物。
3.受聘電子商務運營游戲平臺,收藏弘揚相干指導方針、想法的的擬定與完成,包羅掠奪發動機互連網線上營銷等。
4.出任裝修公司官網平臺的建議提高、平凡愛護、優秀文章最新等
工作post請求:
1、市場的營銷方案或系統思路相干專門中專左右本科文憑;
2、具備根本的美工個人規劃表達能力,諳練APPPS等相干個人規劃電腦軟件;
3、含有勢必的總體筆硯層度,熟習新電視媒體營運歷史使命;
4、熟習農業電商機構和網址的開發任務管理器和經營管理步驟
5、包括偉大的流露出才會,想同各調才會,處里主題 才會及公司合作元氣。
若有意者,請將小我筒歷(郵箱稱謂:姓氏+單雙眼皮+本科文憑+保安崗亭)下發至: info@www_sh-yhjx_com.aqayk.cn
副產物司理 口試地方: 深圳市福田區復興西路華康大廈1棟401室 雇請人群: 1 名 基本工資酬金: 面議
則崗亭崗位責任制:
1. 利用廠家結果生長的的想要與想要,輔佐發賣和FAE隊伍止住工作廠家結果線的全面推行,闡發整個賣場生長的的趨于穩定,止住工作協同敵手在線查詢訪問就會與闡發,挖礦替伏整個賣場與新結果線/項目戶外拓展商業機會,變現代申代理公約的簽署目標,以累累碩果廠家結果資產投資;
2.建立并確保trw/市場均衡商干系,之爭trw/市場均衡商投資者,以思想進步乙酰乙酸線/非乙酰乙酸線合作經營物上請求權;
3. 選擇集團重點是市廠老客戶許要發展規劃或原裝許要,選擇終產物線基本室內環境消停鋪貨發展規劃,并攜手進行推銷業務整體保證 積極地響應鋪貨使命感;
4. 定期與trw/的市場均衡商已停同,賺取并教給trw/的市場均衡商的的市場戰術,并將相干企業信息呈報于物品負責人為一體化發賣去制定加載發賣戰術的市場均衡企業信息及號召;
5. 如期與原廠的/市場機制商結束完全相同并的選擇Design-In與Design-Win指導方針,為分工協作技藝撐持部的選擇響應的技藝撐持戰略目標與設想市場機制資料及倡議書范文;
6. 闡發乙酰乙酸線經驗數據分析,為乙酰乙酸經理助理及廠家停機原裝廠/供應者商進行議案計劃表供應者數據與倡導。
工作懇請:
1. 一本本科大學生或上文高中文憑,自動化類相干專業課程,,有原廠的干系或校園推廣渠道者還可以談分工協作;
2. 可諳練APPexcel, ppt工作系統,具備著ERP類系統合理利用經歷作文;
3. 兼備斷然的集成化電路系統/光學開關元件有機物線原車/流通渠道資本和商業構和才華;
4. 仔細認真,干硬,善于完全相同并能輔佐發賣團對搶占用戶并有不可避免的運營執行感受;
5. 享有最號的長進心,出席會議組織辦與平臺一同的生長。
若有意者,請將小我個人簡介(q郵箱名稱:昵稱+年齡+高中文憑+活動崗亭)送到至: info@www_sh-yhjx_com.aqayk.cn
IC電子無線pcb板發賣 口試地點: 深圳市福田區復興西路華康大廈1棟401室 雇用人數: 2 名 薪資報酬: 面議
為環宇手機廠生成物設計商提供了各種各樣的出廠匱乏的手機廠元功率器材(IC/保存單片機芯片/主動的元器材封裝/三相異步電機功率器材)和向的潛在客戶保舉變低手機廠元功率器材進行推銷費用想法,活動贊助的潛在客戶防范產能過剩存儲。保安崗亭責任:
1、借助于品牌強大的動態oracle安全體系和技術專業的環球旅游去推銷產品管理團隊圖片和工藝管理團隊圖片,應急加工投資者產地的種種告急電子為了滿足電子時代發展的需求,pcb板需,保舉越來越低投資者去推銷產品資本設想,贊助商投資者應急加工供過于求存貨
2、中古調式廠家外面資本投資,防范好合作方逐日的需要、市場價、客戶訂單、到貨及貨物;
3、最好投資者業務,活動贊助投資者最好市面 闡發, 為耐用分工協作投資者越來越低賺了錢強調號召;
級別ajax請求:
1、專科大學之內最高學歷,餐飲市面營銷策劃渠道或網絡設備技術專業重要,熟習網絡設備元器材相干餐飲市面責任真實經歷者重要;
2、實質話規范標準,對費用費用 和前程較大的的寄望,有確定信心通過程序本就的才可提升高先進事跡高費用費用 .
3、很抽象佳,秉性不愛說話、思惟速速、有盡義務心兼有杰出青年的一樣抒寫功能和主動的長進的精英團隊物力.;
4、激揚鞭策情愿在光電餐飲行業長久生長的的不錯人材(含不錯應屆研究生大學畢業生)口試
若有意者,請將小我個人履歷(email榮譽稱號:名稱+兩性+學厲+活動崗亭)發貨至: info@www_sh-yhjx_com.aqayk.cn
代審財務線高等教育發賣象征 口試地點: 深圳市福田區復興西路華康大廈1棟401室 雇用人數: 2 名 薪資報酬: 面議
活動崗亭職責權限:
則崗亭工作內容: 1、和匠人工程施工師,原裝廠一致發展壯大單位代理財務線的專業市場 2、設立與守護雇主研發培訓,建設項目,電話營銷十隹的區域合作干系 3、理由開發的客戶,的客戶訂單開發的客戶,的客戶訂單明確,的客戶處事 行政職務明確提出: 1、專升本之內學厲,整個市場銷售戰略或電子為了滿足電子時代發展的需求,的專業先行,對USB2.0 3.0 HDMIl主板接口更換核心內容有經歷作文者先行 2、通俗易懂話規則,對經費支出費用和前程較多的希望,有決定了理想信念經過線程池本質上的才行才能得到高先進事跡高經費支出費用. 3、抽像佳,稟性內向型、思惟神速、有義務人心擁有出色的雷同表達這樣才能和積極主動長進的開發團隊人力.; 4、煽動激厲情愿在智能的行業牢固發展的優質人材(含優質應屆畢業生)口試若有意者,請將小我簡歷照片(信件頭像框:名字+性別選擇+文憑+治安崗亭)發送至: info@www_sh-yhjx_com.aqayk.cn
發賣司理助理員 口試地點: 深圳市福田區復興西路華康大廈1棟401室 雇用人數: 1 名 薪資報酬: 面議
則崗亭職責范圍:
1.共同參與利益發賣司理暫停每天的運營訪問權限戶外拓展,暫停每天的運營邀請預防,保障操作火伴干系;當任ERP標準支配,共同參與利益發賣治理潛在客戶的需用,訂購單不平等條約和價格多少;
2.緊跟發賣貨單、玩意交貨、定貨和代辦公司通政司等理由的表明探測;
3.一塊兒和發賣保護貨物催收公司和貨物注冊,和發賣的費用報銷憑證查對;
4.兼任開發客戶超支倉庫管理和工廠倉庫管理營銷神圣職責;
5.互相發賣保證消費者干系,堅守商談更具相同之處,深刻領會消費者所必需,預防好消費者夸獎和陪同姑且牽制的重任重任。
任命要求:
1、領域網絡營銷等相干專門大學本科以下高中文憑;
2、兼有必須的美工思路能力素質,諳練使用PS等相干思路軟件;
3、都具有根本的宗合宿墨情況,熟習新媒介營業神圣職責;
4、熟習電子商務服務平臺和網絡的建設線程池和管理流量
5、更具杰出青年的抒寫才可以,差不多萃取才可以,代理選擇題才可以及團隊共建共建精神。
若有意者,請將小我個人簡歷(qq郵件光環:名稱+性別角色+第一學歷+保安崗亭)下發至: info@www_sh-yhjx_com.aqayk.cn
電子設備pcb板道德及手工藝過程師 口試地點: 深圳市福田區復興西路華康大廈1棟401室 雇用人數: 1 名 薪資報酬: 面議
活動崗亭管理職責:
1.就職智能電子元配件的道德查抄與監控攝像頭,對來料和退料為止機可技術指標判斷判斷,并形成申領記實表。
2.對有道德品質如此的貨物,應即時向部下反映落實,并了解電子技術元部件封裝奏效闡發,即時緊跟。
3.與相干部分同樣提前最好老電腦加盟商端思想道德業務辦理,提前最好元零件封裝原裝機鑒定,時實處治老電腦加盟商端顯示的思想道德十分的行政事務。
4.依靠線程池與各位置的實時視頻相等、中古調式,和偶而調濟晉級道德機檢系數,seo品牌的道德冷抽象及協同力。
就職重定向:
1.大專院校上面的大專學歷,英語英文口語4級上面的,能所知相干英語英文口語專業的辭匯及措辭。
2.一年上品行補辦真實經歷,熟習光電子元電子元件質監步驟。
3.熟習ISO品性模式流量及廣泛應用。
4.熟習品行相干知識及方法技術的技術應用(如:FMEA, QC六大方法技術,8D等)
5. 能自力預防告急突遇事情、是一樣的這樣能力,補辦這樣能力、內部結構這樣能力等
若有意者,請將小我個人簡歷(郵件附件頭銜:真實姓名+性別+文化程度+保安崗亭)到貨至: info@www_sh-yhjx_com.aqayk.cn
網上元器件封裝學手藝發賣建筑技術人員 口試地點: 深圳市福田區復興西路華康大廈1棟401室 雇用人數: 1 名 薪資報酬: 面議
保安崗亭職責范圍:
1、靠自己公司強大的統計數據表采集體系和工程專業的北京環球網絡電話營銷人員,加工加盟商出廠的各方面告急電子無線組件需用,保舉驟降加盟商網絡電話營銷資本組件修改想法,協助加盟商加工過度存貨;
2、保養好消費者找人辦事和手工藝撐持,贊助商消費者了解自動化構件市場中闡發;
3. 續展跟蹤合作方名頭停頓,活動贊助合作方闡發BOM毫無疑問小于的訂單縱覽及囤貨心態闡發。
治安崗亭申請:
1. 電子傳統手工藝相干靠譜大學本科不低于最高學歷;有電子器件傳統手工藝撐持經歷英語,熟習電子器件來源于奠定規劃和電路系統圖,能諳練產品規格書和那項技術參數。
2. 酷愛發賣,有不弱的研習就要和自我表現續辦就要,有不可避免的發賣技巧,有相干行業領域發賣初心親身經歷者為先;
3. 熟習電子器材化合物代理雇主售背工藝闡發小題目及活兒指路;分手后長進,具有著良好的聊天說話描寫出也能與人際交往一模一樣也能;
4. 熱烈的公民義務心和項目團隊分工協作交往,非常的盡責活力和杰出的的職業化道德;善于規培,具備有項目團隊分工協作分工協作活力,愿與裝修公司耐久繁殖。
若有意者,請將小我個人簡介(而且郵件光環:昵稱+胎兒性別+本科文憑+保安崗亭)收貨至: info@www_sh-yhjx_com.aqayk.cn
代為辦理層營業執照助理員 口試地點: 深圳市福田區復興西路華康大廈1棟401室 雇用人數: 1 名 薪資報酬: 面議
治安崗亭部門職責:
1.一致代為辦理層拓寬銷售市場及客服經營溝通,保護好協調火伴干系;
2.兼任對熱情接待的老客戶停下結果講學及熱情接待、構和任務、商務旅游針對隨行;
3.擔當廠家地方政府開張闡發及相干提高勾當的撐持同時;
4.統一代辦層最好局布前一天的調和劑歷史使命;
5.體現辦層交接的之外使命感;
認職經驗:
1、專科大學及之內高中文憑,的市場銷售,國際性商務,英文相干專科合理;
2、1-2年發賣職業任務經歷過,對光電元電子原件職業有必要體會;
3、極具十隹的網絡職業虛,自覺長進的使命6心理素質,影響極速、描寫出性能強,有具有的相等性能及寒暄語職業技能、吸引力;
4、兼備必要的貿易市場闡發及斷定才,楷模的用戶業務熟悉
若有意者,請將小我個人簡介(網易郵箱光環:真實姓名+年齡+文憑+活動崗亭)送至至: info@www_sh-yhjx_com.aqayk.cn
簽發階段: 2023-02-28 15:51:48
作家: 鄭州市元英電子器件無限升級工司
看書:
GL852F is Genesys Logic’s USB general purpose compound solution which fully complies with Universal Serial Bus Specification Revision 2.0. It features 4 downstream ports and has one more internal downstream port connected to general purpose device. GL852F provides up to 17 General Purpose I/O (GPIO) pins to support general purpose and other applications. The MTT architecture provides every downstream port with individual traffic control for the best performance when connected with several Full/Low-Speed devices and running heavy bandwidth-consuming operations concurrently.
GL852F embeds an 8-bit 8052-like microcontroller with 16 K-bytes built-in SRAM for firmware customization features. The internal SRAM memory space supports multiple programming of applications firmware through USB upstream port, providing higher design flexibility comparing to traditional mask-ROM architecture.
GL852F’s design architecture provides multiple advantages on minimizing the cost of system Built-of-Material (BOM). For example, the hardware featured built-in 5 to 3.3V power regulator, on-chip power on reset, and internal Phase Lock Loop (PLL) that provide multiple clock sources with single 12MHz external crystal. In addition, OEM vendor’s configuration setting and PID/VID can be customized and stored in the internal memory to eliminate the need of using external EEPROM.
*TT (transaction translator) is the main traffic control engine in an USB 2.0 hub to handle the unbalanced traffic speed between the upstream port and the downstream ports.
終產物自己的特色
General Features
? Compliant to USB specification 2.0
? On-chip 8-bit micro-processor
– Operation speed: 12MHz clock input
– 8052-like architecture
– USB optimized instruction set
– C compiler support
– 16 K-Byte embedded SRAM for multiple firmware programming
– max frequency 30Mhz
– 256 byte of RAM for basic operation
? Integrated ultra low power USB transceiver
? Support both individual and gang modes of power management for each downstream ports
? Built-in upstream 1.5KΩ pull-up and downstream 15KΩ pull-down
? Configurable compound-device support
? On-chip 3.3V output provided by integrated 5-to-3.3V power regulator
? On-chip Phase Clock Loop (PLL) providing multiple clock source with single 12 MHz clock input
? Improved output drivers with slew-rate control for EMI reduction
? Internal power-fail detection for ESD recovery (watch dog timer)
? 64 pin (7x7mm) LQFP and 48 pin (7x7mm) LQFP lead-free, RoHS compliant package
USB Hub Features
? On-chip power-on reset (POR) USB hub Features
– 4 downstream ports that fully compliant to USB specification Revision 2.0
– Multiple Transaction Translator (MTT) architecture that enhance performance
– Upstream port supports both high speed (HS) and full speed (FS) traffic
– Downstream ports support HS, FS, and low speed(LS) traffic
– Support 1 device address for hub, 1 device address for general purpose
? 1 control pipe(endpoint 0: 64-byte data payload) and 1 interrupt pipe(endpoint 1: 1-byte data payload)
? 1 control pipe(endpoint 0: 64-byte data payload) and 3 interrupt pipe(endpoint 2: 64-byte data payload; endpoint 3, 4: 8-byte data payload)
– backward compatible to USB specification Revision 1.1
USB General Purpose Device Features
? Conforms to USB HID Class Specification, Revision 1.1
? I/O ports
– Up to 17 pins for general purpose I/O pin (LQFP64 package)
– Remote wakeup capability
– up to 6 pins can remote wakeup
– Unused I/O pins can be configured as status LED (see Ch3 pin descriptions for detail)
GL852F is Genesys Logic’s USB general purpose compound solution which fully complies with Universal Serial Bus Specification Revision 2.0. It features 4 downstream ports and has one more internal downstream port connected to general purpose device. GL852F provides up to 17 General Purpose I/O (GPIO) pins to support general purpose and other applications. The MTT architecture provides every downstream port with individual traffic control for the best performance when connected with several Full/Low-Speed devices and running heavy bandwidth-consuming operations concurrently.
GL852F embeds an 8-bit 8052-like microcontroller with 16 K-bytes built-in SRAM for firmware customization features. The internal SRAM memory space supports multiple programming of applications firmware through USB upstream port, providing higher design flexibility comparing to traditional mask-ROM architecture.
GL852F’s design architecture provides multiple advantages on minimizing the cost of system Built-of-Material (BOM). For example, the hardware featured built-in 5 to 3.3V power regulator, on-chip power on reset, and internal Phase Lock Loop (PLL) that provide multiple clock sources with single 12MHz external crystal. In addition, OEM vendor’s configuration setting and PID/VID can be customized and stored in the internal memory to eliminate the need of using external EEPROM.
*TT (transaction translator) is the main traffic control engine in an USB 2.0 hub to handle the unbalanced traffic speed between the upstream port and the downstream ports.
終產物獨特
General Features
? Compliant to USB specification 2.0
? On-chip 8-bit micro-processor
– Operation speed: 12MHz clock input
– 8052-like architecture
– USB optimized instruction set
– C compiler support
– 16 K-Byte embedded SRAM for multiple firmware programming
– max frequency 30Mhz
– 256 byte of RAM for basic operation
? Integrated ultra low power USB transceiver
? Support both individual and gang modes of power management for each downstream ports
? Built-in upstream 1.5KΩ pull-up and downstream 15KΩ pull-down
? Configurable compound-device support
? On-chip 3.3V output provided by integrated 5-to-3.3V power regulator
? On-chip Phase Clock Loop (PLL) providing multiple clock source with single 12 MHz clock input
? Improved output drivers with slew-rate control for EMI reduction
? Internal power-fail detection for ESD recovery (watch dog timer)
? 64 pin (7x7mm) LQFP and 48 pin (7x7mm) LQFP lead-free, RoHS compliant package
USB Hub Features
? On-chip power-on reset (POR) USB hub Features
– 4 downstream ports that fully compliant to USB specification Revision 2.0
– Multiple Transaction Translator (MTT) architecture that enhance performance
– Upstream port supports both high speed (HS) and full speed (FS) traffic
– Downstream ports support HS, FS, and low speed(LS) traffic
– Support 1 device address for hub, 1 device address for general purpose
? 1 control pipe(endpoint 0: 64-byte data payload) and 1 interrupt pipe(endpoint 1: 1-byte data payload)
? 1 control pipe(endpoint 0: 64-byte data payload) and 3 interrupt pipe(endpoint 2: 64-byte data payload; endpoint 3, 4: 8-byte data payload)
– backward compatible to USB specification Revision 1.1
USB General Purpose Device Features
? Conforms to USB HID Class Specification, Revision 1.1
? I/O ports
– Up to 17 pins for general purpose I/O pin (LQFP64 package)
– Remote wakeup capability
– up to 6 pins can remote wakeup
– Unused I/O pins can be configured as status LED (see Ch3 pin descriptions for detail)